Mine BitCoin’s with your Papilio! It’s not terribly fast, but it’s still fun to mine your own bitcoins.
Gameduino is a really great Open Source FPGA project put together by James Bowman. It allows you to add graphics and audio to your projects using a nicely documented VGA adapter and Arduino libraries to program it. Take a look at the project page to learn more.
The ESP8266 is a chip that turned a lot of heads recently, stuffing a WiFi radio, TCP/IP stack, and all the required bits to get a microcontroller on the Internet into a tiny, $5 module. It’s an interesting chip, not only because it’s a UART to WiFi module, allowing nearly anything to get on the Internet for $5, but because there’s a user-programmable microcontroller in this board. If only we had an SDK or a few libraries…
The ESP8266 SDK is finally here . A complete SDK for the ESP8266 was just posted to the Expressif forums, along with a VirtualBox image with Ubuntu that includes GCC for the LX106 core used in this module. Included in the SDK are sources for an SSL, JSON, and lwIP library, making this a solution for pretty much everything you would need to do with an Internet of Things thing. As far as LX106 core is concerned, there’s example code for using the spare pins on this board as GPIOs, I2C and SPI busses, and a UART. This turns the ESP8266 into something much better than a UART to WiFi module; now you can create a Internet of Things thing with just $5in hardware. We’d love to see some examples, so put those up on hackaday.io and send them in to the tip line.
Bil Herd, the designer of the Commodore 128, talks about DDS (Direct Digital Synthesis) on a CPLD. There is some excellent information here that is very applicable to the Papilio FPGA. Maybe we can even adopt this project to DesignLab.
“One of the acronyms you may hear thrown around is DDS which stands for Direct Digital Synthesis. DDS can be as simple as taking a digital value — a collection of ones and zeroes — and processing it through a Digital to Analog Converter (DAC) circuit. For example, if the digital source is the output of a counter that counts up to a maximum value and resets then the output of the DAC would be a ramp (analog signal) that increases in voltage until it resets back to its starting voltage…”
Here is a nice technical write-up of the OV7670 camera module that can be purchased on eBay for under $10. We have a Wing that lets you easily connect this camera to the Papilio. There are also VHDL code examples out there on Hamster’s Wiki page. All we need now is to make a DesignLab library for these puppies!
The OV7670 is a low cost image sensor + DSP that can operate at a maximum of 30 fps and 640 x 480 (“VGA”) resolutions, equivalent to 0.3 Megapixels. The captured image can be pre-processed by the DSP before sending it out. This preprocessing can be configured via the Serial Camera Control Bus (SCCB). You can see the full datasheet here.
Cyber Monday only – Pick up a Papilio One 500K for the lowest price we have ever offered – $45.99. We wanted to run a special sale on Cyber Monday as a thank you for all the support we have received from the Papilio community over the years. We just got a big shipment of Papilio One 500K boards so we figured why not give people a chance to buy some at just above what we pay for them. This is a once a year type of a price so if you have a need for some extra Papilio One 500K boards this is your chance!
Free e-book for the ZYNQ FPGA, while this won’t help with the Papilio it is good information for those thinking about getting into the ZYNQ FPGA’s.
This free e-book teaches all about working with the Zynq SoC FPGA, all the way from the “Hello World” basics to asymmetric multiprocessing and the addition of several real-time operating systems (RTOSs). I’m constantly amazed how time manifests its “wibbly-wobbly” nature, as Doctor Who would say. For example, I feel as though I’ve known Adam Taylor for decades — in reality, however, we first came into contact just a couple of years ago… (Cue fuzzy visual effect along with a “going back in time” snippet of music). This all came about shortly after I’d assumed the mantle of “Editor in Chief” at the All Programmable Planet website. Mike Santarini, the editor of Xcell Journal , contacted me to say that a UK engineer called Adam Taylor had written a very interesting article on designing mission-critical state machines, and would I be interested in re-purposing it anywhere. I took a look at the article in Xcell Journal, and it was really good, so I reached out to Adam to ask him if he would care to become a blogger on All Programmable Planet. While we were chatting, we discovered that we had both attended Sheffield Hallam University in England, and we’d even shared some of the same lecturers, although Adam came through 20 years after yours truly. Furthermore, both Adam and I hail from the county of Yorkshire, which is blessed by both Monty Python and the gods. Even though it’s only been a couple of years, Adam and I […]
Here is another new language for high level hardware description. We haven’t used it but this article has a clear description of why a hardware description language that goes further then VHDL or Verilog is needed.
Cx (formerly C~) is a new language for hardware design and verification that is at an intermediate level of abstraction between RTL and HLS. Why is a new language necessary? Because most hardware designers are still stuck with RTL, and because today’s High-Level Synthesis (HLS) does not live up to its promises. Register Transfer Level (RTL) is pretty self-explanatory — you think in terms of registers and how data flows from one register to the next. This closely matches what happens physically, which is another way of saying that it is a very thin layer of abstraction. In turn, this means that you spend a lot of time dealing with implementation-level details that would not concern you if you were working at a higher level of abstraction. VHDL and Verilog are the two main historical languages for describing RTL designs. Both date back to the 1980s and — in the grand scheme of things — have seen little evolution since then. Recent efforts to improve on these two relics include open-source initiatives like MyHDL (RTL in Python) and Chisel (RTL in Scala). MyHDL is led by Jan Decaluwe, while Chisel was created at UC Berkeley with the goal of facilitating processor design. At the other end of the spectrum, we have HLS. We can think of today’s HLS as your manager’s solution. It was sold to her or him (at a premium) as a way to increase productivity and obtain the same performance as RTL. The problem is that […]